module rom_read(
    input sys_clk,
    input sys_rst_n
);

//ROM输出的数据
wire [15:0] do;
//ROM读取地址
reg [15:0] addr;

//生成ROM读取地址
always @(posedge sys_clk) begin
	if(!sys_rst_n)
    	addr <= 16'd0;
    else if(addr < 16'd65535)
    	addr <= addr + 16'd1;
end

rom u_rom_inst0 (
  .doa(do),
  .addra(addr),
  .clka(sys_clk)
);

endmodule
